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    • 专利摘要:
    The present invention relates to a time slot assignment circuit for allocating timeslots to a plurality of modems located in subscriber modem connections of a telephone network matching device. These timeslot allocation circuits include bidirectional buffers 501 and 502 which transfer addresses / data transmitted through the L-bus in a specific direction according to a control signal; A first board timeslot allocator 510 for latching data of a lower byte from a bidirectional buffer to provide first to sixteenth timeslot allocation signals for the first board; The second board timeslot allocator 520 is provided to latch the data of the upper byte from the bidirectional buffer to provide the 17th to 32nd timeslot allocation signals for the second board, thereby treating one subhighway as two boards. In this case, the circuit of the present invention can be used to accurately allocate timeslots.
    公开号:KR19990035430A
    申请号:KR1019970057232
    申请日:1997-10-31
    公开日:1999-05-15
    发明作者:황충환
    申请人:유기범；대우통신 주식회사；
    IPC主号:
    专利说明:

    Multi-frame Synchronous Signal Generator of 560 Modem in High-capacity Communication Processing System
    The present invention relates to a telephone network matching device of a large-capacity communication processing system, and more particularly, to a multi-frame synchronization signal generating device for providing frame synchronization signals to 56K modems of a telephone network matching device.
    In general, a public telephone network is a communication network for transmitting voice signals to other subscribers in a network by performing circuit switching according to call requests of telephone subscribers, and a packet switching network is a communication network for transmitting digital data between computers through packet switching. Although these networks tend to be integrated with each other as the B-ISDN is promoted, they are still composed of individual networks, so the procedures for exchanging services between networks have been very complicated.
    Almost all households and companies are subscribed to the public telephone network and are used most widely, but the service is mainly voice-based telephone service. However, as the information society progresses, data transmission between computers is widely required, and various information providers are on the rise and the demand for access to packet networks is rapidly increasing. Therefore, the type of service connected to the packet switching network has been increased by using the telephone line used in general homes, and for this purpose, an information communication processing system has been introduced into the connection between the public telephone network and the packet network.
    In the conventional communication processing system, as the network evolves, a wide variety of networks, such as an ISDN network, a frame relay network, an ATM network, and the Internet, have been newly established. In order to connect them integrally and to further increase processing capacity, FIG. As shown, it has been improved with a large capacity communication processing system.
    1 is a block diagram illustrating a general mass communication processing system, wherein the mass communication processing system 100 includes a telephone network matching device (TNAS) 110 for connecting to a public telephone network 101, an ISDN network 102, and the like. ISDN matching device (INAS: 130) for connection, packet network matching device (PNAS: 120) for connection with packet communication network 103, ATM network matching device (ANAS :) for connection with high speed (ATM) communication network 104 140), frame network matching device (FNAS: 150) for connection with frame relay network 105, internet matching device (KNAS: 160) for connection with internet 106, high speed switch for connecting each matching device with each other Module (HSSF: 170), unit system management device for network management (LOAMS: 180), etc. to connect subscribers (PC or hightel terminals) connected to public telephone networks or ISDN to information providers (IP) connected to other networks. give.
    Referring to FIG. 1, a telephone network matching device (TNAS) 110 is a high speed switch module 170 for matching a trunk signal with a digital relay line (E1 or T1) of an electronic switchgear, a number system and a signaling method used in a telephone network. ) To connect subscribers connected to the public telephone network (101) to other subscribers such as the packet network (103) by performing the function of connecting the public telephone network (101), collecting statistics and delivering billing information about the user's service use It is a device that connects to the database of the information provider (IP) connected to the network. The conventional telephone network matching device is configured as shown in FIG. 2 so that one telephone network matching device can accommodate 96 channels, and one entire system can accommodate 10 telephone network matching devices to accommodate 960 channels in total. It is supposed to be.
    2. Description of the Related Art A conventional telephone network matching device includes a trunk interface module (TNIF: 210), a subscriber modem connection (TDLA; 220, 221), a high data processing assembly (HDPA; 230, 231), as shown in FIG. , A text service processor assembly (TSPA; 250), and a high speed network adapter (HSNA; 241), the trunk interface module 210 includes a digital T1 trunk interface assembly (Extended T1 trunk Interface Assembly) Extended CEPT trunk Interface Assembly: ETIA / ECIA; 211), Concentration Board (T1 clock Generation & switch Interface / CEPT clock Generation & switch Interface Assembly: TGIA / CGIA; 212), Signal Processing Board (Text Signal Transition Assemply: STA; 213), Universal Signaling Transciever Assembly (USTA; 214), Telephone Network Processor Assembly (TNPA; 215), Alarm Access Control Assembly (AACA) 21 6) to link the users connected to the telephone network of the large capacity communication processing system with the information providers built on the packet network.
    Referring to FIG. 2, the service processing unit (TSPA) 250 is duplexed into two boards, and the high speed switching interface unit HSNA 240 and 241 and the plurality of subscribers for interworking with the high speed switching fabric HSHS 170. It is responsible for controlling the modem connection unit (TDLA: 220, 221) and the data processing unit (HDPA: 230, 231). That is, the main functions of the service processing unit (TSPA) 250 provide a telephone network subscriber interface and management, data processing of subscribers and information providers, high speed switch interface (HSNA) interworking, and service control and self maintenance.
    The signal of the public telephone network subscriber is designated by the trunk matching module (TNIF: 210), and is transmitted to the data processing unit (HDPA: 230, 231) at the RS-232C level through the corresponding modem of the subscriber modem connection (TDLA: 220, 221). In this case, one subscriber modem connection unit (TDLA) accommodates 16 channels, so two boards are connected to each other in order to process one subhighway (32 channels), and one board is connected to 32 channels for one data processing unit (HDPA). I can accept it. Therefore, six subscriber modem connections (TDLA) and three data processing units (HDPA) are required to process 96 channels (three subhighways).
    The data processor (HDPA: 230, 231) transmits and receives data in units of 32 channels / PBA, and transmits X.3 parameters to the received data to the service processor (TSPA: 250) through the transmission and reception queues, which are determined in 132 byte units, respectively. do. The service processing unit (TSPA) 250 transmits packet related information to the high speed switch interface unit (HSNA: 240, 241), and the high speed switch interface unit (HSNA: 240, 241) transmits this data to the high speed switch module (HSSF: 170 of FIG. 1). Through the packet network matching device (PNAS: 120 of Figure 1) through.
    Motorola's MC68030 / 50MHz is used as the main processor of the service processor (TSPA: 250) and Motorola's MC68360, an IPC (Inter Processor Communication) dedicated communication processor, is used for data communication with the data processor (HDPA: 230,231). Data is transmitted in an interrupt manner through 1M bytes of common memory. The data processor (HDPA: 230, 231) uses Motorola's MC68360 as the main processor and controls four slave processors. The main processor of the data processor (HDPA: 230, 231) transmits and receives data in 2 Mbps serial communication between the slave and the service processor (TSPA: 250).
    In FIG. 2, the digital relay line matching board (ETIA / ECIA: 211) matches 4T1 or 3E1. When the 4T1 is matched, the “ETIA” board is used and when the 3E1 is matched, the “ECIA” board is used. The aggregation board (TGIA / CGIA: 212)) receives the reference clock to generate the system clock, handles the subhighway switching function, and the signal service board (USTA: 214) is an R2 MFC and DTMF known as a standard for inter-station relay. It handles tones and performs services related to tones. The alarm access control unit (AACA: 216) collects hardware alarms, determines a status, reports the maintenance alarm, and performs a matching function with the maintenance processor. The telephone network matching processor (TNPA: 215) communicates with the service processor (TSPA) 250 and controls each device.
    In Figure 2, the telephone network matching module (TNIF: 210) provides access to the public telephone network 101 through a PCM transmission line of 1.544 Mbps T1 or 2.048 Mbps E1, collects outgoing subscriber numbers by R2 MFC signaling, and subscriber information. Is transmitted to the service processing unit (TSPA) 250. When the reception of the service processing unit TSPA 250 is confirmed, the service processing unit TSPA is connected to the information provider IP connected to the packet network matching device 120 via the high speed switch module HSSF 170. That is, the telephone network matching device 200-1 to 200-10 connects modems in response to various modems of telephone subscribers, multiplexing function of digital data, communication protocol processing function, raw charging data collection function, Handle each of the subsystem maintenance itself.
    In such a telephone network matching device, a plurality of modems are accommodated in one subscriber modem connection unit. Recently, 56K modems are required due to the development of modems, and thus, a device for providing multi-frame synchronization to 56K modems is required.
    Accordingly, an object of the present invention is to provide an apparatus for generating a multi-frame synchronization signal required for a plurality of 56K modems in a telephone network matching device of a large-capacity communication processing system.
    In order to achieve the above object, the apparatus of the present invention is a large-capacity communication processing system for providing a multi-frame synchronization signal to a predetermined number of 56K modems by receiving a 2M clock and a frame synchronization (FS) clock from a trunk matching unit. A first divider configured to receive the 2M clock and the frame synchronization clock and output a predetermined divided clock; A delay unit for delaying the frame synchronization clock; A second divider which receives the delayed frame synchronization clock and the 2M clock and outputs a predetermined divided clock; A first decoder for decoding the output of the first divider and outputting a predetermined number of timeslots; A second decoder for decoding the output of the second divider and outputting a predetermined number of timeslots; And a multiframe synchronous output unit for outputting a predetermined number of multiframe synchronous signals by combining the outputs of the first decoder and the second decoder.
    1 is a block diagram showing the overall configuration of a large capacity communication processing system;
    2 is a block diagram showing a conventional telephone network matching device in a mass communication processing system;
    3 is a block diagram showing a telephone network matching device to which the present invention is applied;
    4 is a block diagram of an apparatus for generating a multiframe synchronous signal according to the present invention;
    5 is a timing diagram of a frame synchronization signal generated in accordance with the present invention.
    * Explanation of symbols for main parts of the drawings
    41: clock input 42: delay
    43: first divider 44: second divider
    45: first decoder 46: second decoder
    47: Multi-frame synchronous output 48a, 48b: 56K modem
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    As shown in FIG. 3, the telephone network matching device to which the present invention is applied includes a trunk interface unit (TNIA; 310) that is directly connected to the public telephone network 101 and accommodates 4E1. Telephone Processing Interface Assembly (TPIA; 312), Subscriber Modem Interface (Text Data Interface Assembly: TDIA; 314), Highly Data Processing Assembly (HDPA: 316), Text Service Processor Assembly (TSPA; 318), High Speed Network Adapter (HSNA; 319a, 319b).
    Referring to FIG. 3, since the subscriber modem connection unit 314 capable of accommodating 16 channels can process one subhighway (SHW: 32 channels) in two sets, 2x4 = 8 boards are used to process 4E1. In addition, the data processing unit 316 correspondingly requires four boards (32 channels / board). The service processor 318 is redundant to improve reliability, and the high speed switch interface units 319a and 319b may also be duplicated.
    In addition, the trunk interface unit (TNIA) 310 may be connected to the public telephone network 101 to accommodate 4E1, and switch the time slot to connect four subhighways (SHW) with the processor interface unit 312 to establish a digital trunk interface. (TLI) and link signal matching (LSI) functions. The trunk interface unit (TNIA: 310) is connected to the processor interface unit 312 and the L bus 301 and is controlled by the processor interface unit (TPIA: 312) of the public telephone network (PSTN: 101) using the CEPT method. It matches with relay circuit between stations and transmits / receives signal information of relay line using tone and R2 signaling. At this time, the transmission speed of the CEPT method (E1) is "2.048Mbps", and the line code "HDB3" is used.
    The trunk interface (TNIA: 310) also accepts R2 signals, provides a ring back tone, and incorporates a network synchronizer to synchronize the transmission bits of the trunk line. The 2.048 MHz clock extracted from is used, and the local clock generated by the network synchronization circuit of the trunk interface 310 is 16.384 MHz. That is, the trunk interface unit 310 is provided with a network synchronization circuit to generate 16.384 MHz synchronized with 2.048 MHz extracted from the trunk line, and then divides it and is required by the processor interface unit 312 and the subscriber modem connection unit 314. Various clocks (4M, 2M, 8KHz clock) are provided.
    Looking at the transmission operation is performed through the trunk interface 310, four sub-highway (SHW0 to SHW3) data consisting of 32 time slots input from the digital switch of the processor interface (TPIA: 312) is the trunk interface unit Channel matching is performed at the digital switch MT8980 of step 310 and input to the CEPT framer. The CEPT framer of the trunk interface unit 310 formats the subhighway data (SHW Data) and the signal data (Signalling Data) to the CEPT format, and performs HDB3 line coding at the line interface unit and then converts the unipolar-bipolar (U / B) into Output to CEPT type PCM trunk line.
    On the contrary, the reception process receives the CEPT format data from the PCM relay line, switches the time slots in the trunk interface 310 to access the subhighway data, and processes various alarms, error detection, and signaling. The frame synchronization (FS: 8KHz) clock and the 4MHz clock required are generated by the network synchronization circuit of the trunk interface 310.
    Meanwhile, the link signaling matching (LSI) function of the trunk interface unit (TNIA) 310 is an R2 MFC signal transmission / reception and a tone supply function. When the trunk interface unit 310 receives a scissors request from the trunk line, the trunk interface unit 310 transmits the scissors request information to the processor interface unit TPIA: 312, and the processor interface unit TPIA: 312 receives the request from the trunk. The input data channel is connected to the R2 signal receiving processor of the trunk interface unit. The trunk interface unit (TNIA) 310 receives a signal input from the trunk line, translates the signal, and transmits the signal to the processor interface unit (TPIA: 312). The trunk interface unit (TNIA) 310 provides forward and backward signals required by the R2 signaling method. In addition, the trunk interface 310 performs a tone providing function. Since only a ring back tone is required due to system characteristics, the trunk interface unit 310 continuously allocates a tone channel.
    The processor interface unit TPIA: 312 processes control processing through the L-bus 301 for various events generated by the trunk interface unit TNIA: 310 and the subscriber modem connection unit TDIA: 314. It has a function of collecting various alarms of a device. In addition, a call-related communication is performed through the S bus 302 with a service processor (TSPA) 318, which is a higher processor. The processor interface unit TPIA 312 employs a Motorola multi-protocol processor (MC68302 IMP) to reduce and simplify circuit, power, and component density. Motorola's MC68302 is a high-performance processor that has a variety of peripheral devices that require a control structure in the existing 68000 CPU, and basically provides various interfaces required by a conventional processor.
    Meanwhile, according to the present invention, an apparatus for providing a multi-frame synchronization signal to a 56K modem includes a clock input unit 41, a delay unit 42 for delaying a frame synchronization signal, and a first divider as shown in FIG. And a second divider, a first decoder, a second decoder, and a multiframe synchronization output unit to provide a multiframe synchronization signal to 16 56K modems. At this time, since the sub-highway is composed of 32 channels, two multi-frame synchronization signal generators are required to accommodate 32 56K modems. That is, the first generation device receives the 2M clock and the frame synchronization signal and provides the multiframe synchronization signal to the 0th to 15th modems, and the second generation device receives the 2M clock and the frame synchronization signal and the 16th to 31st signals. Provides a multiframe sync signal to the modem.
    Referring to FIG. 4, the clock input unit is configured as a buffer to stabilize the clock (2 more accurately 2.048 MHz) and the frame synchronization clock (FS: about 8 KHz) input from the trunk matching unit, and the delay unit is an 8-bit shift register ( 74164) to delay the frame synchronization signal.
    The first divider consists of two synchronous binary counters 74163 that can be preset and reset to divide 2M clocks to output 128K, 64K, 32K, 16K, and 8K clocks, and the first decoder to a 4 to 16 demultiplexer 74154. To make 16 timeslots.
    The second divider is configured in the same manner as the first divider and divides the 2M clock by the delayed frame synchronization clock to output 128K, 64K, 32K, 16K, and 8K clocks, and the second decoder 4 to 16 demultiplexer 74154. To make 16 timeslots.
    The multiframe synchronous output unit is implemented with 16 oragates, and outputs 16 multiframe synchronous signals by combining 16 time slots respectively output by the first decoder and the second decoder.
    As such, the timings of the 16 multiframe synchronization signals generated according to the present invention are shown in FIG. 5. Referring to FIG. 5, it can be seen that after the frame synchronization clock is generated, 16 multiframe synchronization signals are sequentially generated and provided to the 16 modems. In FIG. 5, "[I] 2MCLK" represents a 2M clock input from the trunk matching unit, "[I] FS" is a frame synchronization signal, and "[I] EN / ODD" is a signal for distinguishing two boards. [0] 0 to [O] 15 are multi-frame synchronization signals for providing to modems 0 to 15. [I] If EN / ODD is low, outputs multiframe synchronous signal for modems 0 to 15. If [I] EN / ODD is high, outputs multiframe synchronous signal for modems 16 to 31. do.
    As described above, the apparatus for generating a multiframe synchronous signal of the mass communication processing system according to the present invention can provide a multiframe synchronous signal required by a 56K modem with a very simple circuit.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] A large capacity communication processing system for receiving a 2M clock and a frame synchronization (FS) clock from a trunk matching unit and providing a multiframe synchronization signal to a predetermined number of 56K modems,
    A first divider 43 which receives the 2M clock and the frame synchronous clock and outputs a predetermined divided clock;
    A delay unit 42 for delaying the frame synchronization clock;
    A second divider 44 for receiving the delayed frame synchronization clock and the 2M clock and outputting a predetermined divided clock;
    A first decoder (45) for decoding the output of the first divider and outputting a predetermined number of timeslots;
    A second decoder 46 for decoding the output of the second divider and outputting a predetermined number of timeslots; And
    And a multi-frame synchronous output unit (47) for outputting a predetermined number of multi-frame synchronous signals by combining the outputs of the first decoder and the second decoder.
    [2" claim-type="Currently amended] 2. The apparatus of claim 1, wherein the synchronization signal generator further comprises an input unit 41 for receiving and stabilizing the 2M clock and the frame sync (FS) clock. Frame sync signal generator.
    [3" claim-type="Currently amended] The 56K modem multi-frame according to claim 1, wherein the first and second decoders 45 and 46 are composed of 4 to 16 demultiplexers 74154 to output 16 timeslots. Synchronous signal generator.
    [4" claim-type="Currently amended] 2. The apparatus for generating a multi-frame synchronization signal of a 56K modem in a high-capacity communication processing system according to claim 1, wherein the multi-frame synchronization output unit (47) is implemented with 16 oragates.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-31|Application filed by 유기범, 대우통신 주식회사
    1997-10-31|Priority to KR1019970057232A
    1999-05-15|Publication of KR19990035430A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970057232A|KR19990035430A|1997-10-31|1997-10-31|Multi-frame Synchronous Signal Generator of 560 Modem in High-capacity Communication Processing System|
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